Download 1364.1-2002 IEEE Standard for Verilog Register Transfer PDF

General syntax and semantics for VerilogR HDL-based RTL synthesis are defined during this commonplace.

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Extra info for 1364.1-2002 IEEE Standard for Verilog Register Transfer Level Synthesis

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5 Gate and switch level modeling 42 Copyright © 2002 IEEE. All rights reserved. 1 Gate and switch declaration syntax gate_instantiation ::= cmos_switchtype [delay3] cmos_switch_instance { , cmos_switch_instance } ; | enable_gatetype [drive_strength] [delay3] enable_gate_instance { , enable_gate_instance} ; | mos_switchtype [delay3] mos_switch_instance { , mos_switch_instance } ; | n_input_gatetype [drive_strength] [delay2] n_input_gate_instance { , n_input_gate_instance } ; | n_output_gatetype [drive_strength] [delay2] n_output_gate_instance { , n_output_gate_instance } ; | pass_en_switchtype [delay3] pass_enable_switch_instance { , pass_enable_switch_instance } ; | pass_switchtype pass_switch_instance { , pass_switch_instance } ; | pulldown [pulldown_strength] pull_gate_instance { , pull_gate_instance } ; | pullup [pullup_strength] pull_gate_instance { , pull_gate_instance } ; cmos_switch_instance ::= [name_of_gate_instance] ( output_terminal , input_terminal , ncontrol_terminal , pcontrol_terminal ) enable_gate_instance ::= [name_of_gate_instance] ( output_terminal , input_terminal , enable_terminal ) mos_switch_instance ::= [name_of_gate_instance] ( output_terminal , input_terminal , enable_terminal ) n_input_gate_instance ::= [name_of_gate_instance] ( output_terminal , input_terminal { , input_terminal } ) n_output_gate_instance ::= [name_of_gate_instance] ( output_terminal { , output_terminal } , input_terminal ) pass_switch_instance ::= [name_of_gate_instance] ( inout_terminal , inout_terminal ) pass_enable_switch_instance ::= [name_of_gate_instance] ( inout_terminal , inout_terminal , enable_terminal ) pull_gate_instance ::= [name_of_gate_instance] ( output_terminal ) name_of_gate_instance ::= gate_instance_identifier [ range ] pulldown_strength ::= ( strength0 , strength1 ) | ( strength1 , strength0 ) | ( strength0 ) pullup_strength ::= ( strength0 , strength1 ) | ( strength1 , strength0 ) | ( strength1 ) enable_terminal ::= expression inout_terminal ::= net_lvalue input_terminal ::= expression Copyright © 2002 IEEE.

Unsigned_number] exp [ sign ] unsigned_number exp ::= e | E decimal_number ::= unsigned_number | [ size ] decimal_base unsigned_number | [ size ] decimal_base x_digit { _ } | [ size ] decimal_base z_digit { _ } binary_number ::= [ size ] binary_base binary_value octal_number ::= [ size ] octal_base octal_value hex_number ::= [ size ] hex_base hex_value sign ::= + | size ::= non_zero_unsigned_number non_zero_unsigned_number ::= non_zero_decimal_digit { _ | decimal_digit } Copyright © 2002 IEEE. All rights reserved.

All rights reserved. 1-2002 IEEE STANDARD FOR VERILOG® genvar_function_call ::= genvar_function_identifier { attribute_instance } ( constant_expression { , constant_expression } ) conditional_expression ::= expression1 ? { attribute_instance }expression2 : expression3 constant_expression ::= constant_primary | unary_operator { attribute_instance } constant_primary | constant_expression binary_operator { attribute_instance } constant_expression | constant_expression ? { attribute_instance } constant_expression : constant_expression | string expression ::= primary | unary_operator { attribute_instance } primary | expression binary_operator { attribute_instance } expression | conditional_expression | string module_path_conditional_expression ::= module_path_expression ?

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