By Ken Arnold
Ken Arnold is an skilled embedded structures dressmaker and president of HiTech apparatus, Inc., an embedded platforms layout enterprise positioned in San Diego, California. He additionally teaches classes in embedded and software program layout on the college of California-San Diego.
Gives the reader an built-in hardware/software method of embedded controller design
Stresses a "worst case" layout procedure for the tough environments within which embedded structures are frequently used
Includes layout examples to make vital ideas come alive
Read or Download Embedded Controller Hardware Design PDF
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Extra info for Embedded Controller Hardware Design
Not all SFRs are bit addressable, and not all bit addresses are used in most processors. Bit Number Internal Data Memory 7F 30 2F Bit Addressable 20 1F 00 Figure 2-11: Bit addressable space in the internal data memory. Byte Addr 7 6 5 4 3 2 1 0 2F 2E 2D 2C 2B 2A 29 28 27 26 25 24 23 21 22 20 7F 77 6F 67 5F 57 4F 47 3F 37 2F 27 1F 17 0F 07 7E 76 6E 66 5E 56 4E 46 3E 36 2E 26 1E 16 0E 06 7D 75 6D 65 5D 55 4D 45 3D 35 2D 25 1D 15 0D 05 7C 74 6C 64 5C 54 4C 44 3C 34 2C 24 1C 14 0C 04 7B 73 6B 63 5B 53 4B 43 3B 33 2B 23 1B 13 0B 03 7A 72 6A 62 5A 52 4A 42 3A 32 2A 22 1A 12 0A 02 79 71 69 61 59 51 49 41 39 31 29 21 19 11 09 01 78 70 68 60 58 50 48 40 38 30 28 20 18 10 08 00 MOV C<->bit# CLR bit# SETB bit# CPL bit# JB bit#, addr JNB bit#, addr Bit addressable memory allows the manipulation and test of individual bits, which is a very common operation in embedded systems.
The 8031 contains Memory FFFF Figure 2-9: Data memory 128 bytes of internal data address spaces in the 8051. RAM and 20 special function registers (SFRs), while most External Data other processor family variants Internal Special Memory Data Function include an additional 128 bytes Memory Registers /RD or See below See separate address map of internal data memory over/WR Pulse FF FF lapped with the SFR addresses. Low MOV @R0/1 MOV 80-FF 80 7F 80 MOV 00-7F Data Memory 00 Some SFRs are also bit addressable MOVX a 0000 The 8051 family devices have two data memories, internal and external.
The purpose for using tri-state logic is to allow multiple devices to share wires by taking turns one at a time. This may sound a bit silly, but it is just one form of multiplexing, or sharing a resource that needs to be allocated among multiple devices. When the resource is a collection of parallel data wires, referred to as a data bus, and the bus is shared by multiple microcomputer CPU and peripheral devices transferring information one at a time in sequence, it is referred to as a multiplexed data bus.